The present invention relates generally to thin film field-effect transistors and, more particularly, to such transistors that may be fabricated without stringent alignment between a source and drain electrode configuration and a gate electrode.
Thin film field-effect transistors (FETs) are semiconductor devices, which include, as basic elements, a single, thin (e.g., less than about 1 micron) semiconductor layer and various electrodes; namely, source and drain electrodes, and a gate electrode for controlling conduction between the source and drain electrodes. The source and drain electrodes each adjoin one major side of the semiconductor layer, while the gate electrode is insulatingly spaced from an opposite, major side of the semiconductor layer.
In the fabrication of the foregoing, thin film FETs, it is desired that both the source and drain electrodes overlap the gate electrode (as viewed from a direction orthogonal to the semiconductor layer), in order to ensure high transconductance between the source and drain electrodes. However, the source-to-gate and drain-to-gate overlaps are limited in extent to prevent the formation of large source-to-gate and drain-to-gate capacitances, which would create an undesired signal path between the source and drain electrodes. Accordingly, optimum FET performance has been achieved through stringent alignment of the source and drain electrodes (which are typically formed with a single mask) to the gate electrode, so that the source-to-gate and drain-to-gate overlaps fall within a fairly small range of, typically, 0.5 to 1.5 microns. In a practical manufacturing environment, however, such a stringent alignment requirement is not easily complied with. As a consequence, a typical manufacturing yield of a batch of thin film FETs tends to be lower than desirable, the yield being increasingly lower as the aggregate area occupied by the FETs increases.